There is a seemingly ever-increasing demand for higher levels of integration of semiconductor circuits. Sub-micron images, now being conventionally employed in semiconductor structures, rely upon state-of-the-art photolithographic processes and tooling. More exotic exposure systems, i.e., X-ray, E-beam, etc., are being utilized to obtain even smaller feature sizes. To further increase the density of semiconductor structures, the prior art has integrated devices within the depths of the substrate, in addition to its planar upper surface. Dynamic random access memories, today, commonly employ "trenches" for memory cell capacitances. In addition, slots or trenches are used to isolate individual devices within a monolithic circuit.
To improve monolithic densities, it has been proposed that active semiconductor structures be emplaced within slots/trenches in a substrate. Standard photolithographic techniques are not directly applicable to "personalization" of such concave surface areas. Other methods have been used to accomplish some level of device masking in concave substrate areas. In U.S. Pat. No. 4,303,933 to Horng et al., the fact that a grown oxide's thickness is dependent upon the level of doping of an underlying silicon layer is employed to enable a trench sidewall opening to be produced. Horng et al. show that a low temperature oxidation results in the formation of a thick oxide over a heavily doped N+ region and a thinner oxide over a lightly doped N+ region. When the oxides are subsequently etched, the thinner region is removed first, thereby opening a sidewall area for subsequent processing. A similar teaching appears in an article entitled "Method of Producing Transistors With Optimum Base Contact", by Berger et al., IBM Technical Disclosure Bulletin, Vol. 23, No. 4, Sept. 1980, pp. 1487, 1488.
In U.S. Pat. No. 4,534,824 to Chen, in-trench masking is disclosed in combination with angled implantation to form an in-trench structure. A in-trench mask is shown in U.S. Pat. No. 4,984,048 to Sagara et al., however details are not provided as to how the mask is achieved. Lammert, in U.S. Pat. No. 4,711,017, discloses a method of providing a device within a trench wherein an N+ region is formed at the bottom of the trench and subsequently driven into the substrate. The trench is then further etched to enable the addition of further internal features.
In publication 28622, entitled "A Method of Sidewall Image Transfer Utilizing the Polyimide-Nitride Material Interaction", Research Disclosure, February, 1988, No. 286, Mason Publications Ltd., England, a polyimide is used to form defined vertical sidewalls for the fabrication of spacers. No patterning of the polyimide, or nitride layers emplaced thereover, is described.
Conformal organic layers have been employed to aid in the creation of vertical semiconductor structures. One such organic material is poly-p-xylylene or "parylene" which is the generic name for members of a polymer series produced by the Union Carbide Corporation. Such a use of Parylene is disclosed in U.S. Pat. No. 4,838,991 to Cote et al. More general prior art teachings relating to conformal polymeric coatings and paraxylylene can be found in the following U.S. Pat. Nos.: 3,900,600 to Spaulding, 3,297,465 to Connell et al., 3,607,365 to Lindlof, 3,392,051 to Caswell et al., 3,399,124 to Gilch, and 3,342,754 to Gorham.
In summary, the prior art shows various materials that can be employed to form and coat concave trench-like structures in semiconductor substrates. It further shows that patterns can be produced in such trench areas, and teaches that such patterns can be produced if the underlying semiconductor materials are appropriately processed (e.g., to enable different oxide rates of growth). It is highly desirable that any process used to "personalize" a trench structure be independent of the underlying semiconductor structure, insofar as the processing steps are concerned.
Accordingly, it is an object of this invention to provide an improved method for providing a mask structure within a concave semiconductor structure.
It is another object of this invention to provide an improved masking process for concave semiconductor structures wherein the process is substantially independent of underlying semiconductor compositions.
It is still another object of this invention to provide an improved masking technique for trench-like structures in a semiconductor wafer, wherein trench sidewalls can be selectively masked and subsequently processed for the incorporation of device structures therein.